1. Field of the Invention
The present invention relates to an address converter of a semiconductor device and a semiconductor memory device having the same and, more particularly, to an address converter of a semiconductor device in which different addresses are internally designated whenever electrical power is applied even though a same address is externally designated, and a semiconductor memory device having the same.
2. Description of the Related Art
A semiconductor device needs an address to read and write data. The address is used to designate a certain memory cell in a memory cell array of a semiconductor memory device so that data can be inputted or outputted. The address is allocated by an external control device.
The address of the semiconductor memory device comprises a combination of a row address for selecting a row of the memory cell array and a column address for selecting a column of the memory cell array.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device.
In the case of a synchronous memory device such as a synchronous dynamic random access memory (SDRAM), the semiconductor memory device receives a clock CLK from an external portion and uses it as a reference for its operation.
An address register 24 receives an address ADD and a clock CLK from an external portion, classifies the address ADD into a row address RA and a column address CA, and synchronizes them with the clock CLK and outputs them to a row decoder 22 and a column decoder 23, respectively.
A command decoder 25 receives a command corn and outputs a row address strobe (RAS) signal and a CAS before RAS (CBR) signal for an active operation to the row decoder 22. The command decoder 25 outputs a column address strobe (CAS) signal to the column decoder 23 for a read or write operation. The command decoder 25 outputs a write enable signal WE to a data IO portion 26 to control data input and output.
The row decoder 22 receives the RAS signal from the command decoder 25 and performs an active operation to receive the row address RA from the address register 24 to thereby designate a certain word line among a plurality of word lines of the memory cell array 21. The row decoder 22 receives the CBR signal from the command decoder 25 to have the memory cell array 21 to perform a refresh operation.
The column decoder 23 is controlled by the CAS signal applied from the command decoder 25 during the read or write operation, and receives the column address CA from the address register 24 to designate a certain bit line among a plurality of bit lines of the memory cell array 21.
The memory cell array 21 includes a plurality of word lines arranged in a transverse direction, a plurality of bit lines arranged in a vertical direction, and memory cells arranged at crossing points between the word lines and the bit lines. The memory cell array 21 further includes a plurality of sense amplifiers for detecting and amplifying data.
In the memory cell array 21, when a memory cell arranged at a crossing point between the word line selected by the row decoder 22 and the bit line selected by the column decoder 23 is selected, the sense amplifier outputs data DQi of the selected memory cell to the external portion or amplifies and stores data DQi inputted from the external portion in the memory cell array according to the read or write command applied from the command decoder 25.
The data IO portion 26 receives the write enable signal WE from the command decoder 25 to receive/output data from/to the memory cell arranged at a crossing point between the word line designated by the row decoder 22 and the bit line designated by the column decoder 23.
A mode setting portion 27 receives a mode setting signal MRS from the command decoder 25 when a power stabilization signal (not shown) is generated after electrical power is applied to the semiconductor memory device. The mode setting portion 27 combines a setting signal applied in the form of the address ADD from the external portion to store a default setting of the semiconductor memory device in response to the mode setting signal MRS. That is, the mode setting portion 27 receives a setting signal through a terminal to which the address ADD is inputted, and performs the default setting of the semiconductor memory device when the electrical power is applied to the semiconductor memory device.
The semiconductor device having the above described memory structure is activated from a designated initial address in address order and then performs the read or write operation when the electrical power is applied, but loses all of its information when the electrical power is not applied. When the electrical power is applied again so that a process for storing data is performed, the read or write operation is repeated in same address order as the previous process. Thus, the use frequency of a certain memory cell increases, and so the memory cell having high use frequency is stressed over time. Due to the hot carrier effect which may occur in a hyperfine process, the stress applied to the memory cell becomes more serious, resulting in a bad influence upon the lifespan and reliability of the semiconductor memory device.
The same phenomenon happens in a flash memory which is a non-volatile memory device, but the flash memory has a feature for storing information even though the electrical power is not applied and thus using this feature, address information of the memory cells used in a previous process is stored. When the electrical power is applied again, addresses of the used memory cells which are stored in a certain region are read, and a write process is allocated from a non-used address.
According to Japanese Patent Publication No. 2003-249087, in a computer system with a central processing device, a memory device and an address converting circuit, when reset, using, as a mask, a plurality of certain bits of a start address outputted from a central processing unit, the start address is converted. Japanese Patent Publication No. 2003-249087 is characterized in that designated addresses of ROM and RAM are converted and a discrete converting circuit is arranged outside the memory device.
According to Japanese Patent Publican No. 2003-249087, a non-volatile memory device includes a reset address setting circuit to designate a discretionary certain address as an initial start address when the electrical power is applied or after reset. Japanese Patent Publican No. 2003-249087 uses the feature of the non-volatile memory device for reset address setting circuit to designate a certain address, and it cannot be used in a volatile memory device.
In the conventional semiconductor devices described above, since the initial address is designated in the same way, the use frequency of the certain memory cell increases, and the memory cell having the high use frequency gets stress, resulting in the short lifespan and low reliability of the semiconductor device. In order to resolve the above problems, the discrete address converting device is arranged outside the semiconductor memory device or the non-volatile memory device is used to convert the initial address, but it cannot be used in the volatile memory device.